SiP-id™ Design Flow
SiP-id™ stands for System-in-Package – Intelligent Design. The solution consists of an enhanced reference flow that includes IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package- and system-level design into a unified and automated flow. By deploying the SiP-id™ methodology, chip designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools. The end result is a vast reduction in the time needed to design and verify ultra-complex SiP packages.
It is our intention to offer all ASE customers a set of efficient tools where designers can freely experiment with designs which can go beyond the current packaging limits. This set of design tools are available to eligible customers immediately. However, some of the proprietary libraries and design rules will be subject to an agreement with ASE. It is our belief that IoT, AI, VR, AR, EV and all future applications will demand more SiPs and modules. This is an ongoing effort by ASE, not only to develop fanout (such as Fan-Out Chip on Substrate, FOCoS), panel fanout, embedded substrates, 2.5D, but also to making design tools more user friendly, up-to-date and efficient.
What is required to start a package design with SiP-id™, DRC deck is required for fan-out design and 3D DRC deck, for SiP design. The customer can engage our in-house engineering to begin the process.