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Heterogeneous Integration (HI)

The semiconductor industry is facing a new era in which device scaling and cost reduction will no longer continue on the path followed for the past few decades. Packing more transistors on a monolithic IC is becoming more difficult and expensive at each node. Semiconductor companies are now looking for technology solutions to bridge the gap and improve cost-performance, while at the same time adding more functionality through integration. Integrating all the functions into a single chip (known as system on a chip (SoC)) present many challenges that include higher costs and design complexities. An attractive alternative is heterogeneous integration that uses advanced packaging technology to integrate devices which could be separately designed and manufactured by the most suitable process technology in the most optimized way.

What is Heterogeneous Integration (HI)?

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly (System-in-Package, SiP) that, in the aggregate, provides enhanced functionality and improved operating characteristics. Source: Heterogeneous Integration Roadmap 2019 Edition CHAPTER 1 OVERVIEW.

The combined components can vary in system level (e.g., pre-assembled package or subsystem), functionality (e.g., specialized processors, DRAM , flash memory, surface mount device (SMD) resistor/capacitor/inductor, filters, connectors, MEMS device, sensors) and technologies (e.g., one optimized for die size with another one optimized for low power). The overall idea behind heterogeneous integration is to integrate multiple die in the same package. This enables the package to perform a specific and advanced function in a small form factor.

Heterogeneous Components


System-in-Package (SiP)

Advantages of Applying Heterogeneous Integration

Conventionally, the semiconductor industry tried to squeeze everything into one monolithic chip. However, it’s getting so expensive and the chip is getting so big. Heterogeneous integration tackles the age-old issue by combining chips with different process nodes and technologies. This technology enables the continued increase in functional density and decrease in cost per function required to maintain the progress in cost and performance for electronics. Heterogeneous Integration is essential to maintain the pace of progress with higher performance, lower latency, smaller size, lighter weight, lower power requirement per function, and lower cost.

Technology Building Blocks for Heterogeneous Integration

HI Technology Building Blocks

HI Technology Building Blocks (continued)

Heterogeneous Integration Roadmap (HIR)

Emerging technologies—such as AI, 5G, edge, cloud, and data center, autonomous vehicles and wearable technology— hold great promise for improving the lives of individuals across the globe. The HIR maps out the future of system-level integration and the potential advanced packaging solutions necessary for implementing the emerging technologies.

ASE's Dr. William (Bill) Chen is leading the HIR initiative alongside Dr. Bill Bottoms of 3MTS (IEEE EPS), Tom Salmon (SEMI), S. Iyer (IEEE EDS), A. Helmy (IEEE Photonics), and Ravi Mahajan (ASME EPPD). The Heterogeneous Integration Roadmap is the result of dedicated collaboration and enormous effort by ASE contributors including Rich Rice, CP Hung, John Hunt and Mark Gerber, as well as the many contributors from across the electronics community. The 2019 edition of the Heterogeneous Integration Roadmap includes 22 chapters and can be downloaded by visiting https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html.


日月光的異質整合團隊,擁有多年領先業界之封裝經驗及系統級封裝(SiP)技術,因應人工智慧、物聯網和行動裝置小型化的需求,日月光系統級封裝技術能提供小體積,大容量且低功耗控制器與感測器的整合;此外,也發展多元商業模式,積極推動系統級封裝生態圈,日月光以創新技術解決方案系統級封裝(SiP)及感測器封裝(MEMS),結合銅打線、覆晶封裝、晶圓級封裝、扇出型晶圓級封裝(Fan Out)、2.5D/3D IC、基板與內埋式晶片封裝,提供行動裝置、物聯網、高效能運算與車聯網市場需求。