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TSV-Interposer Integration

Si interposers with Through Silicon Vias (TSVs) have been many investigations into the manufacturing and characterization in ASE, the bonding methods for die to die attach, the handling of thin wafers, the novel assembly processes, and the testing methodologies and reliability of micro-bumps. With the high-density routing (L/S: 0.4/0.4um) and more than 200k micro bumps in one package, 2.5D technology enables the high bandwidth communication, homogeneous & heterogeneous chip integration and small form factor. 2.5D technology has already been a proven technology by many customers and IC vendors.



Application
Features
  • GPU (Visual Reality, VR)
  • Networking (Switch)
  • FPGA
  • HPC
  • Artificial Intelligence (AI)

The detailed SEM photo illustrates the cross-section view of a 2.5D technology. SEM photo below is the cross section across the GPU, micro-bump interface, interposer, C4 bump interface, substrate, and BGA balls.

  • High-density routing (L/S: 0.4/0.4um)
  • More than 200k micro bumps (55mm X 55mm)
  • Homogeneous & heterogeneous chip integration
  • HBM/HMC to ASIC
  • Small form factor
  • JEDEC MSL4 certified

Capabilities

Throughout the program, reliability was a significant focus. Package level reliability tests were carried out following JEDEC MSL pre-conditioning, Temperature Cycle Test (TCT), Highly Accelerated Temperature and Humidity Stress Test (HAST) and High Temperature Storage Test (HTST). Board-level reliability tests, including TCT, vibration test, mechanical shock test and monotonic bend test were designed, performed and assessed. Electrostatic discharge (ESD) control was confirmed for the new assembly and handling flows. Power cycling (PwrCyc) and TSV stress migration (SM) were employed to guarantee the new physical structure of the interposer and electro-migration (EM) was verified for the new interfaces.







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