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Trends and Development in Heterogeneous Integration: Advancing the Smart Digital Age with System-in-Package and Chiplet Technologies

Heterogeneous integration (HI) is fast becoming a key driver of semiconductor development due to its ability to scale the number of individual chips onto a miniaturized system-in-package that enhances functionality, achieves higher efficiency, and even reduces power consumption. At the recently concluded SEMICON CHINA 2021 Advanced Packaging Forum, Dr KK Kuo (VP, R&D at ASE Jiangsu) delivered an insightful presentation on the trends and developments in Heterogeneous Integration and Fan-out Wafer Level Packaging.  At present, HI technologies are enabled by: system-in-package (SiP) packaging that allows miniaturization and a higher level of integration; 2D/3D IC packaging that delivers higher bandwidth and lower latency; and Fan In/Fan Out Wafer Level Packaging (WLP) that achieves higher performance and higher density. To provide IC designers a robust automated design solution that addresses heterogeneous integration parameters, ASE collaborated with Deca Technologies and Siemens Digital Industries Software to launch the APDK™ (Adaptive Patterning® Design Kit). The APDK methodology provides IC designers a library of templates, extensive automation that guides the designer from initial layout to Adaptive Patterning simulation, to final design sign-off using Siemens’ Calibre software. ASE’s experience in volume production of highly integrated SiP including its M-series Fan-out WLP technology, demonstrates the company’s leadership in advancing device and system performance. Another trend in HI is the development of chiplets, a relatively inexpensive method that can quickly assemble independent IC chiplets (smaller and usually less expensive chips) through die-to-die interconnect, that when combined, accelerates the performance and power efficiency of the integrated package. An example of a chiplet architecture is the integration of CPU cores, memory ICs and 3D stacking technology to vastly improve bandwidth and interconnect quality. Chiplet designs are gaining popularity as the approach shortens the design leadtime and lowers the cost threshold – IC designers do not need to fabricate new chips using expensive nodes and fab processes. This methodology is now widely applied in designing high-end processors, FPGA and networking ICs. SPIL (a member of the ASE Technology Holding Co), has developed several fan-out packaging technologies to support chiplets including; Flip Chip Multi-Chip Module (FCMCM), 2.1D/2.5D/3D, Fan Out Multi-Chip Module (FOMCM), Fan-Out Embedded Bridge (FOEB) and Embedded Multi-die Interconnect Bridge (EMIB). The high acceptance rate of these process technologies are contributing to lower manufacturing costs and improving speed to market. Innovation in the packaging world is game changing, and the combined synergy from ASE, SPIL and USI is raising the company’s competitive edge and industry R&D standards. ASE is also building strong supply partnerships and expanding market opportunities to provide solutions that deliver high performance, speed and efficiency. We sincerely believe that our Heterogeneous Integration journey will contribute immensely to the next generation of smart digital applications. Source: SPIL, 2020 VLSI Circuit Symposium

Heterogeneous Integration Fuels the Future

IntroductionMoore’s Law has driven the semiconductor industry for decades, but in recent years, there has been deceleration in terms of performance and economic benefit. The exponential cost of silicon scaling has created an inflection point for the industry, and that is driving the development of More-Than-Moore technologies to augment device functionality and strengthen system performance. A Brief History of Semiconductor RoadmapsThe semiconductor industry comprises highly specialized yet closely interdependent companies that must stay on top of technology and market application trends to keep developments on track. As the industry grew, it became imperative by the 1990s that global semiconductor companies must work together to ensure progress was heading in the same direction. In 1991, semiconductor companies in the United States, under the auspices of the Semiconductor Industry Association (SIA), first established the National Technology Roadmap for Semiconductors or NTRS. By 1998, roadmapping efforts had expanded when companies from Japan, Europe, Korea, and Taiwan joined the NTRS effort, and together with SIA, they formed the International Technology Roadmap for Semiconductors (ITRS). SIA brought ITRS to a close in 2015, and that is when the Heterogeneous Integration Roadmap, or HIR, was initiated. Heterogeneous Integration Will Take Us ForwardHeterogeneous Integration refers to the integration of separately manufactured components into a higher-level assembly system-in-package (SiP) that in the aggregate provides enhanced functionality and improved operational characteristics. It is now the key technology direction going forward, driving the pace of advancement for greater intelligence and connectivity, higher bandwidth and performance, and lower latency and power per function, all at a more manageable cost. The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics that identifies technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration among industry, academia, and government to accelerate progress. HIR is designed to provide long term continuity and a broad technology base. It is organized with sponsorship by three IEEE Technical Societies (Electronics Packaging Society, Electron Devices Society, and Photonics Society) together with SEMI and ASME Electronics and Photonics Packaging Division (EPPD). Technology takes a long time to develop and mature, and increasingly involves the collective knowledge from overlapping fields. It is therefore essential to set goals for the long-run and cover as many subjects and fields as possible, related to heterogeneous integration. As the industry enters the digital transformation and exascale computing era, massive compute with frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising the issue of operational and storing cost of the data. The advent of artificial intelligence (AI) and machine learning (ML) requires large amounts of data to be processed and is driving an entirely new computing paradigm from edge computing to cloud to data centers. Traditional IC design trends are to pack more transistors on a monolithic die or system-on-chip (SoC) at each process node, resulting in difficult chip scaling for the integration of analog, logic, and memory circuits. The heterogeneous integration approach is die-partitioning or chiplets, which offers a compelling value proposition for yield improvement, IP reuse, performance, and cost optimization, as well as time-to-market reduction. Chiplet integration has the potential to allow the integration of disparate technologies from multiple suppliers to provide more flexible mix-and-match systems to accelerate performance and improve power efficiency without requiring the deployment of these technologies across an entire SoC simultaneously. Chiplet solutions start with internal designs within a system integrator. However, as IP interface standards are developed, the commercialization of chiplets in the market will proliferate. Heterogeneous Integration through chiplets will play a critical role for future HPC and AI/ML applications.ASE System-in-Package (SiP) Demonstrates Heterogeneous Integration. As a leading semiconductor packaging, test, and system service provider, ASE has heavily invested in both chip-level (SoC) package integration and system-level integration. The development of cutting-edge heterogeneous integration technologies addresses functional areas from silicon integration, power integration, optical integration to system integration that form the backbone of many electronic components, subsystems, and electronics products. ASE has developed and offers a wide portfolio of Si-level integration technology solutions, from low- to high-density chiplet integration including flip-chip multi-chip-module (FC-MCM), fanout chip-on-substrate (FOCoS), and 3D IC. The advanced FOCoS technology can provide short die-to-die connection and high interconnections (10,000s), redistribution layers (RDL) with 2µm line/space, and up to four layers for chip-first and chip-last packaging processes. It produces a lower-cost solution with improved electrical performance compared to a 2.5D Si interposer solution due to the elimination of Si through silicon via (TSV) processes and reduced insertion loss. ASE is evolving this advanced packaging platform to meet application demands for HPC and AI/ML applications. A Smarter, Healthier, More Efficient FutureLooking further into 2021 and beyond, key developments in packaging that create higher performance systems and utilize less power will be deployed. System performance will continue the pace of Moore’s Law era, albeit in a different way than with the previous total reliance on semiconductor chip lithography and SoC integration. There is tremendous optimism that innovations in the IC packaging industry will continue on a heterogeneous integration journey. Discovery, creativity, innovation, and very importantly, collaboration – will enable applications that make our world smarter, healthier, and infinitely more efficient. This article has been adapted from the blog article ‘The Future is Heterogeneous Integration’ by Dr Bill Chen. To read the full article, please click on https://www.3dincites.com/2021/01/the-future-is-heterogeneous-integration/

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Heterogeneous Integration Fuels the Future

IntroductionMoore’s Law has driven the semiconductor industry for decades, but in recent years, there has been deceleration in terms of performance and economic benefit. The exponential cost of silicon scaling has created an inflection point for the industry, and that is driving the development of More-Than-Moore technologies to augment device functionality and strengthen system performance. A Brief History of Semiconductor RoadmapsThe semiconductor industry comprises highly specialized yet closely interdependent companies that must stay on top of technology and market application trends to keep developments on track. As the industry grew, it became imperative by the 1990s that global semiconductor companies must work together to ensure progress was heading in the same direction. In 1991, semiconductor companies in the United States, under the auspices of the Semiconductor Industry Association (SIA), first established the National Technology Roadmap for Semiconductors or NTRS. By 1998, roadmapping efforts had expanded when companies from Japan, Europe, Korea, and Taiwan joined the NTRS effort, and together with SIA, they formed the International Technology Roadmap for Semiconductors (ITRS). SIA brought ITRS to a close in 2015, and that is when the Heterogeneous Integration Roadmap, or HIR, was initiated. Heterogeneous Integration Will Take Us ForwardHeterogeneous Integration refers to the integration of separately manufactured components into a higher-level assembly system-in-package (SiP) that in the aggregate provides enhanced functionality and improved operational characteristics. It is now the key technology direction going forward, driving the pace of advancement for greater intelligence and connectivity, higher bandwidth and performance, and lower latency and power per function, all at a more manageable cost. The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics that identifies technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration among industry, academia, and government to accelerate progress. HIR is designed to provide long term continuity and a broad technology base. It is organized with sponsorship by three IEEE Technical Societies (Electronics Packaging Society, Electron Devices Society, and Photonics Society) together with SEMI and ASME Electronics and Photonics Packaging Division (EPPD). Technology takes a long time to develop and mature, and increasingly involves the collective knowledge from overlapping fields. It is therefore essential to set goals for the long-run and cover as many subjects and fields as possible, related to heterogeneous integration. As the industry enters the digital transformation and exascale computing era, massive compute with frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising the issue of operational and storing cost of the data. The advent of artificial intelligence (AI) and machine learning (ML) requires large amounts of data to be processed and is driving an entirely new computing paradigm from edge computing to cloud to data centers. Traditional IC design trends are to pack more transistors on a monolithic die or system-on-chip (SoC) at each process node, resulting in difficult chip scaling for the integration of analog, logic, and memory circuits. The heterogeneous integration approach is die-partitioning or chiplets, which offers a compelling value proposition for yield improvement, IP reuse, performance, and cost optimization, as well as time-to-market reduction. Chiplet integration has the potential to allow the integration of disparate technologies from multiple suppliers to provide more flexible mix-and-match systems to accelerate performance and improve power efficiency without requiring the deployment of these technologies across an entire SoC simultaneously. Chiplet solutions start with internal designs within a system integrator. However, as IP interface standards are developed, the commercialization of chiplets in the market will proliferate. Heterogeneous Integration through chiplets will play a critical role for future HPC and AI/ML applications.ASE System-in-Package (SiP) Demonstrates Heterogeneous Integration. As a leading semiconductor packaging, test, and system service provider, ASE has heavily invested in both chip-level (SoC) package integration and system-level integration. The development of cutting-edge heterogeneous integration technologies addresses functional areas from silicon integration, power integration, optical integration to system integration that form the backbone of many electronic components, subsystems, and electronics products. ASE has developed and offers a wide portfolio of Si-level integration technology solutions, from low- to high-density chiplet integration including flip-chip multi-chip-module (FC-MCM), fanout chip-on-substrate (FOCoS), and 3D IC. The advanced FOCoS technology can provide short die-to-die connection and high interconnections (10,000s), redistribution layers (RDL) with 2µm line/space, and up to four layers for chip-first and chip-last packaging processes. It produces a lower-cost solution with improved electrical performance compared to a 2.5D Si interposer solution due to the elimination of Si through silicon via (TSV) processes and reduced insertion loss. ASE is evolving this advanced packaging platform to meet application demands for HPC and AI/ML applications. A Smarter, Healthier, More Efficient FutureLooking further into 2021 and beyond, key developments in packaging that create higher performance systems and utilize less power will be deployed. System performance will continue the pace of Moore’s Law era, albeit in a different way than with the previous total reliance on semiconductor chip lithography and SoC integration. There is tremendous optimism that innovations in the IC packaging industry will continue on a heterogeneous integration journey. Discovery, creativity, innovation, and very importantly, collaboration – will enable applications that make our world smarter, healthier, and infinitely more efficient. This article has been adapted from the blog article ‘The Future is Heterogeneous Integration’ by Dr Bill Chen. To read the full article, please click on https://www.3dincites.com/2021/01/the-future-is-heterogeneous-integration/

Trends and Development in Heterogeneous Integration: Advancing the Smart Digital Age with System-in-Package and Chiplet Technologies

Heterogeneous integration (HI) is fast becoming a key driver of semiconductor development due to its ability to scale the number of individual chips onto a miniaturized system-in-package that enhances functionality, achieves higher efficiency, and even reduces power consumption. At the recently concluded SEMICON CHINA 2021 Advanced Packaging Forum, Dr KK Kuo (VP, R&D at ASE Jiangsu) delivered an insightful presentation on the trends and developments in Heterogeneous Integration and Fan-out Wafer Level Packaging.  At present, HI technologies are enabled by: system-in-package (SiP) packaging that allows miniaturization and a higher level of integration; 2D/3D IC packaging that delivers higher bandwidth and lower latency; and Fan In/Fan Out Wafer Level Packaging (WLP) that achieves higher performance and higher density. To provide IC designers a robust automated design solution that addresses heterogeneous integration parameters, ASE collaborated with Deca Technologies and Siemens Digital Industries Software to launch the APDK™ (Adaptive Patterning® Design Kit). The APDK methodology provides IC designers a library of templates, extensive automation that guides the designer from initial layout to Adaptive Patterning simulation, to final design sign-off using Siemens’ Calibre software. ASE’s experience in volume production of highly integrated SiP including its M-series Fan-out WLP technology, demonstrates the company’s leadership in advancing device and system performance. Another trend in HI is the development of chiplets, a relatively inexpensive method that can quickly assemble independent IC chiplets (smaller and usually less expensive chips) through die-to-die interconnect, that when combined, accelerates the performance and power efficiency of the integrated package. An example of a chiplet architecture is the integration of CPU cores, memory ICs and 3D stacking technology to vastly improve bandwidth and interconnect quality. Chiplet designs are gaining popularity as the approach shortens the design leadtime and lowers the cost threshold – IC designers do not need to fabricate new chips using expensive nodes and fab processes. This methodology is now widely applied in designing high-end processors, FPGA and networking ICs. SPIL (a member of the ASE Technology Holding Co), has developed several fan-out packaging technologies to support chiplets including; Flip Chip Multi-Chip Module (FCMCM), 2.1D/2.5D/3D, Fan Out Multi-Chip Module (FOMCM), Fan-Out Embedded Bridge (FOEB) and Embedded Multi-die Interconnect Bridge (EMIB). The high acceptance rate of these process technologies are contributing to lower manufacturing costs and improving speed to market. Innovation in the packaging world is game changing, and the combined synergy from ASE, SPIL and USI is raising the company’s competitive edge and industry R&D standards. ASE is also building strong supply partnerships and expanding market opportunities to provide solutions that deliver high performance, speed and efficiency. We sincerely believe that our Heterogeneous Integration journey will contribute immensely to the next generation of smart digital applications. Source: SPIL, 2020 VLSI Circuit Symposium

2.5D vs Fan-out Chip on Substrate

The demand for high bandwidth and high-performance applications such as networking, AI computing and GPU IC chips are driving innovative developments in advanced IC packaging. Heterogeneous integration enables the integration of multiple chips using fine line/space interconnect packaging technology.Heterogeneous integration packaging solutions offered in the market today include, through silicon via (TSV) interposer technology: 2.5D IC packaging and re-distribution layer (RDL) fan-out process better known as fan-out chip on substrate package (FOCoS).FOCoS fabrication methods include chip first and chip last processes. We have utilized FEA simulations to examine the warpage, ELK layer crack risk, interconnection/RDL trace broken risk, and board level solder joint reliability of three package types: 2.5D IC, chip-first FOCoS and chip-last FOCoS. The validity of the simulation model is confirmed by comparing the numerical results for the warpage and thermal mechanical deformation of chip-last FOCoS with the experimental observations by advanced Metrology Analyzer (aMA) system. Further CFD simulations are then performed to investigate the heat dissipation performance of the three package types.We have investigated the warpage and in-plane thermal deformation of packages at various environment temperatures. Three-dimensional numerical models have been developed to compare the mechanical and thermal performance. The warpage and inplane thermal deformation of the FEM model has been validated with the measurement result. Having validated the FEM model, this study applied the FEA investigations to package types' comparison and examine the influence of the chip-last FOCoS wafer level underfill material properties on the D2D area interconnection copper trace reliability.The results from the numerical simulation are as follows:The warpage of the two FOCoS package types are lower than 2.5D IC due to smaller CTE mismatch between combo die and stack-up substrate. Besides, the chip-last FOCoS has the lowest warpage quantity with the contribution of wafer level underfill.The ELK stresses of FOCoS for both chip-first and chip-last are lower than 2.5D package, because RDL/PI layers are the effective buffering to reduce ELK layer stress.The solder ball with maximum CSED occurs on the outermost solder joint located on the package edge of the solder joint top side, i.e. substrate side, surface. All these three packages have insignificant difference on CSED. It means that the board level TCT performance is similar because the equivalent CTE of all the package types are similar.The interconnection copper trace stress of 2.5D package has lower stress than others due to smaller localized CTE mismatch to reduce copper trace stress.The wafer level underfill type D with higher Tg and lower CTE has lowest stress, which could enhance copper trace reliability performance.2.5D IC, chip-first FOCoS and chip-last FOCoS have similar thermal performance and all of them are good enough for high power applications.More information can be found in the ECTC article entitled "A comparative study of 2.5D and fan-out chip on substrate: Chip first and chip last".

Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-out Chip Last Packages

In recent years, Fan-Out (FO) packages have become widely used in handheld, mobile consumer and internet of things (IoT) devices. FO packaging allows greater I/O density as well as the ability to pack multiple components in the same package compared to conventional wafer level chip scale package (WLCSP). Several types of FO packaging are offered in the market today, for example; embedded wafer level BGA (eWLB), M-Series™ as well as a flip chip based structure referred to as Fan-out Chip-Last Package (FOCLP).We have investigated the mechanical and thermal performance of these FO packages. Finite element analyses were carried out to examine mechanical performance metrics, including warpage, stress in the extreme low-k (ELK) interconnect and board level solder joint reliability. Thermal simulations were completed to compare the thermal dissipation differences among the FO package types. We also applied the optical profile measurement facility advanced metrology analyzer (aMA) to investigate the correlation between in plane strain and out-of plan warpage of fan-out packages at various environment temperatures. A three-dimensional computational model has been developed to compare mechanical and thermal performance of different fan-out package types.The aMA measurement results have shown that the warpage quantity of M-Series™ structure is lower than eWLB. Besides, the dimension change of eWLB is higher than M-Series™. The performance of the fan-out packages FE model has been verified by comparing the simulation results for the package in-plan dimension change with those obtained experimentally.In addition, the numerical simulation results show that:The maximum warpage of all types are less than 25um. FOCLP has higher warpage due to high CTE mismatch between thin coreless substrate and compound. Besides, the M-Series™ has lower warpage quantity because backside coating film help to balance CTE mismatch to reduce warpage.The ELK stress of FOCLP and M-Series™ are similar and lower than other package types. This is the result of the molding compound RDL above the copper pillars acting as a stress buffer.The solder ball with maximum Creep strain energy density (CSED) occurs on the outermost solder joint located on package edge at theUBM edge. eWLB and M-Series™ packages have similar CSED, while FOCLP has lowest CSEDvalue. This is due to less CTE mismatch between the PCB and the FOCLP package.The different types of fan-out packages have similar thermal performance and, overall, dissipate heat better than WLCSP.More information can be found in the ECTC article entitled "Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-out Chip Last Packages".

Business un-usual: Resilience in the face of a pandemic.

Early 2020 was certainly unforgettable for many of us in Asia. Around that time, the COVID-19 (known then as the Wuhan virus, or simply coronavirus) caseload was already spiraling out of control in Wuhan, the city where the virus was first detected at a seafood market. Wuhan, the epicenter of the outbreak, was locked down by the Chinese government on January 23rd. Our company’s management mobile group chat was abuzz non-stop about the situation in China, especially in and around our facilities. It was the Spring break where many Chinese traditionally return to their hometowns and many businesses remain shut for the celebration. No one knew exactly how widespread the disease had affected populations beyond Wuhan, but somehow we knew that we have to plan for the worst.The ASE crisis management mechanism was immediately triggered. We established a special task force and developed an advanced data management system to coordinate COVID-19 measures across all ASE locations.  Each factory had set up a ‘command room’ to deploy the company’s business continuity plan across the entire organization. Appointed personnel were actively communicating with local authorities to keep lockstep with the situation, as well as to implement measures based on the governments’ advisories. During that time, the situation in China was especially intense, as the disease continues to spread to other cities.Our top priority was to ensure the safety of our employees. With this in mind, our procurement teams became very busy scouting for essential personal protective equipment, especially surgical masks. Masks were suddenly in high demand and the price correspondingly shot up. Our facilities outside China also rallied to help our colleagues secure 3-ply masks.ASE mask factoryMask-wearing reduces the spread of viral particles from asymptomatic carriers and plays a key role in mitigating the spread of COVID-19. ASE has invested in the production of high-quality surgical masks at ASE Kaohsiung. ASE medical grade masks have received certification from Taiwan’s Ministry of Health and Welfare.  - protecting the health of our employees  - ensuring easy access to masksASESG reusable masksAt ASE Singapore, employees are provided custom designed ASE-logo reusable masks. The fabric masks are made from high quality material and each has an insert for filters that retain their efficacy after repeated washes. To ensure that customers are kept abreast of the developments and to minimize any disruptions, we posted daily updates on each facility on our official website during the height of the pandemic. In parallel, individual sites kept their respective customers updated frequently and drew up contingency plans to mitigate impact to customers.Importantly, we all recognized the need to play our part to prevent the spread of the disease. Temperature checks, travel history and health declaration became mandatory for all employees and visitors to ASE premises. Social distancing emerged as a new buzz phrase, but it is proving an effective preventive measure. Thanks to modern technology, we were able to conduct video and conference calls with colleagues, customers and suppliers with little disruption to business. In the months of March and April, many countries worldwide imposed some sort of lockdowns as the outbreak worsened outside China. As a result, many of our offices rolled out ‘work from home’ schemes, as well as alternate team work arrangements to minimize large group gatherings. Today, our operations in Asia have returned to normalcy. Our US and Europe colleagues, however, are still requested to work from home until the situation improves.The pandemic has caused huge disruptions and forced us to rethink how we work, interact, and socialize. For now, we’re all staying put where we are, and hopefully spending quality time with family while keeping ourselves healthy, both physically and mentally. Until we find a vaccine or a cure, we have to embrace the new norm as best as we can.Wash your handsWear a maskWiden your space 
Jennifer Yuen 9/15/2020 News

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