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Evelyn Lu

Director, Marketing and Communications

Enabling next-generation System Integration with scalable SiP solutions for Healthcare Applications

Semiconductor miniaturization and chip integration trends are driving greater industry focus on system-in-package (SiP) developments. SiP is a cost effective package integration technology that features higher performance and reduces time to market. These advantages allow chip companies to design electronic products that integrate more functions and develop new technology applications. Dr CP Hung, vice president, ASE Corporate R&D offers an insight on the application of SiP technology in healthcare electronics.Continuous Glucose MonitorA continuous glucose monitor (CGM) is a small wearable device that tracks blood sugar levels throughout the day and help detects trends and patterns. The data allows doctors and patients to better manage diabetic conditions. A CGM consists of a sensor, data transmitter and receiver, and the results are tracked via a monitor or a smartphone app.ASE’s SiP technology supports the integration of different microcontrollers (MCUs), application-specific integrated circuits (ASICs), antennas and sensors that control all the functions in a CGM, onto a single package structure. The packaging process offers miniaturization without compromising the performance of the device.In Vitro Diagnostics In vitro diagnostics (IVD) are tests performed on samples, such as mucus or blood, taken from the human body to help detect diseases or other conditions. The information obtained from analysis of such samples are used by health practitioners to monitor a patient’s overall health, and to treat or prevent diseases. A variety of IVD devices and systems are used by healthcare professionals in clinics, labs and hospitals, as well as by consumers at home.Complex IVD module designs are made possible with SiP technology processes that allow the integration of the bio-sensor chips and the microfluid receptacle through the use of customized molding techniques.Sensor ApplicationsWafer-level SiP technology is another packaging technique that applies through-silicon via (TSV) chip-scale package (CSP) processes to reduce the XY area size by 30% compared with traditional quad flat no-lead (QFN) packaging. At the same time, the electrical performance of the package structure is enhanced through lowering the resistance level by almost 80%.Sensor Hub A sensor hub is a microcontroller unit that integrates and processes data from various sensors. Through-silicon via (TSV) and chip-to-wafer (C2W) bonding are techniques used to design chips inside sensor hubs. Other methodology of chip design include placing ASIC and sensor components side-by-side, or placing a TSV die on top of another standard die.Wafer-level SiP technology can be applied in many types of sensor packages including 3D inertial, gas, temperature and humidity sensors. The data in the diagram shows that WL SiP package sizes can be reduced by between 25% to 77% compared with traditional packaging processes.ASE provides a complete suite of packaging and test services – from package design, functional simulation to testing, verification, volume production and final testing. ASE continues to provide industry-leading system-in-package integration solutions to help customers speed up product development.

Unlocking More in Wearable Devices

The rapid development of smart wearable devices is driving improvements in sensor and packaging technology that offers unprecedented business opportunities for the semiconductor industry. System-in-Package (SiP), a packaging technique that enables highly integrated miniaturized systems through the integration of different sensors and chips with multiple functions (MCU, memory and more) within a small form factor, is fast becoming the preferred packaging solution for future wearable devices.SiP technology is designed to enable dense circuitry, which in turn allows miniaturization, lowers power consumption, improves radio frequency and maximizes functional capacity. Additional IC testing and testing of aged units further ensure chip performance and consistent quality. From smart watches, smart glasses to Bluetooth headsets, SiP integration technology is enabling chip designers to customize solutions easily. For example, more than 30 components can be integrated onto a single chip with a size of 4mmx8mm or 4.55mmx9mm, vastly reducing the product size and its overall weight by 1 gm or more.Watch MoreSiP Solutions for HearablesIn the designing of hearable devices, miniaturization is achieved through SiP packaging because it reduces the motherboard area and mitigates radio frequency and audio interference. Features like acoustic design and active noise control can be easily adjusted thereby, freeing up more space to optimize the acoustic cavity design to produce better sound quality and increase battery life. The addition of a built-in antenna using an AiP (Antenna-in Package) solution can further optimize the isolation between audio and radio frequency.ASE’s SiP solution provides several advantages to customers:Reduces inventory and material inspections, simplifying assembly and testing processes.Reduces assembly manpower and work processes.Provides customized solutions that meets product design and acoustic specifications.Reduces time-to-market and provides a cost competitive solution.The ASE SiP ToolboxASE offers customers a complete SiP solution covering:Module design and developmentSiP development board and antenna designPCBA software and hardware integration, development and debuggingVolume assembly and testing solutions

Premiering ASE Technology and Solutions at 2021 WSCE China

At this week's World Semiconductor Conference held in Nanjing, China, ASE, together with SPIL and USI, showcased the company's complete solution platform that encompasses its leadership in System-in-Package (SiP) and Advanced Packaging. ASE is a primary architect in Heterogeneous Integration which is helping to drive developments in HPC, IoT and automotive electronics.Unleashing the synergy of ASE, SPIL and USI to drive chip performance and solve chip design challengesChip First and Chip Last Fan-Out Packaging solution platform which allows the designing of high performance computing chips with high density2.5D/3D IC packaging solutions supporting high bandwidth and low latencyDesign and manufacturing experience in chiplet packaging technology at SPIL – the portfolio includes FO-MCM+EHS-FCBGA(Fan-Out Multi-Chip-Module + Exposed Heat Sink-Flip Chip BGA), HBW-POP(High Bandwidth Package-on-Package), FO-POP(Fan-Out Package-on-Package), ETS-SiP(Embedded Trace Substrate-System in Package), FO-SD(Fan Out-Single Die)USI’s proven miniaturization capabilities that support the wireless and mobile communication markets including LTE Cat.1 communication module, TWS Bluetooth audio module, wireless communication module, dual-core wireless microcontroller (MCU) equipped with Bluetooth®5, OpenThread and ZigBee®3.0. USI’s solutions are widely applied in devices with small footprints such as fitness watches and wearable products, TWS headsets, mobile devices, routers, industrial IoT, healthcare devices and tracking devicesEnabling a Smarter World We are accelerating a smarter world through our advanced packaging and module solutions.Complete Solutions for Smart Factories, Smart Cities and IoT-SiP (ASE, SPIL) + System-on-Modules (USI)Safety and Reliability in Smart Automotive. Wire bond, flip chip, WLCSP, SiP and discrete packaging portfolio (ASE, SPIL) + automotive power control modules (USI)ISE Labs China is our first engineering center in China that has received VDA6.3 and AECQ certification and mass production qualifications for automotive electronic chips.Smart Wearables. ASE’s TWS SiP modules enable more functions to be integrated onto a limited space. DockSiP and MicroSiP packaging solutions support miniaturization and ease of integration. Other solutions include integrated MEMS & Sensors, low-power antenna packaging and double-sided thin wireless communications.Playing a Leading Role through Innovation, Investment and CollaborationInvited to speak at the Innovation Summit, Dr. KK Kuo (VP, R&D ASE CHINA) provided his insights on the industry landscape and remarked, ‘The 5G+AI digital era and the evolution of Moore's Law has accelerated the demand for chip miniaturization, high performance and low power consuming chips that contribute to continuous breakthroughs in advanced packaging technology. Heterogeneous integration applications are on track to demonstrate explosive growth in the future, driven by rapid growth in high-performance computing (HPC), 5G, application processor engines (APC), automotive radars, radio frequency, audio, power management integrated circuits (PMIC) and many other applications. High-density packaging will increase in importance and advanced packaging and SiP will help drive the development for the next generation of semiconductor technologies. ASE Group will continue to play a leading role through innovation, prudent investments and industry collaboration.’

Trends and Development in Heterogeneous Integration: Advancing the Smart Digital Age with System-in-Package and Chiplet Technologies

Heterogeneous integration (HI) is fast becoming a key driver of semiconductor development due to its ability to scale the number of individual chips onto a miniaturized system-in-package that enhances functionality, achieves higher efficiency, and even reduces power consumption. At the recently concluded SEMICON CHINA 2021 Advanced Packaging Forum, Dr KK Kuo (VP, R&D at ASE Jiangsu) delivered an insightful presentation on the trends and developments in Heterogeneous Integration and Fan-out Wafer Level Packaging.At present, HI technologies are enabled by: system-in-package (SiP) packaging that allows miniaturization and a higher level of integration; 2D/3D IC packaging that delivers higher bandwidth and lower latency; and Fan In/Fan Out Wafer Level Packaging (WLP) that achieves higher performance and higher density. To provide IC designers a robust automated design solution that addresses heterogeneous integration parameters, ASE collaborated with Deca Technologies and Siemens Digital Industries Software to launch the APDK™ (Adaptive Patterning® Design Kit). The APDK methodology provides IC designers a library of templates, extensive automation that guides the designer from initial layout to Adaptive Patterning simulation, to final design sign-off using Siemens’ Calibre software. ASE’s experience in volume production of highly integrated SiP including its M-series Fan-out WLP technology, demonstrates the company’s leadership in advancing device and system performance.Another trend in HI is the development of chiplets, a relatively inexpensive method that can quickly assemble independent IC chiplets (smaller and usually less expensive chips) through die-to-die interconnect, that when combined, accelerates the performance and power efficiency of the integrated package. An example of a chiplet architecture is the integration of CPU cores, memory ICs and 3D stacking technology to vastly improve bandwidth and interconnect quality. Chiplet designs are gaining popularity as the approach shortens the design leadtime and lowers the cost threshold – IC designers do not need to fabricate new chips using expensive nodes and fab processes. This methodology is now widely applied in designing high-end processors, FPGA and networking ICs.SPIL (a member of the ASE Technology Holding Co), has developed several fan-out packaging technologies to support chiplets including; Flip Chip Multi-Chip Module (FCMCM), 2.1D/2.5D/3D, Fan Out Multi-Chip Module (FOMCM), Fan-Out Embedded Bridge (FOEB) and Embedded Multi-die Interconnect Bridge (EMIB). The high acceptance rate of these process technologies are contributing to lower manufacturing costs and improving speed to market.Innovation in the packaging world is game changing, and the combined synergy from ASE, SPIL and USI is raising the company’s competitive edge and industry R&D standards. ASE is also building strong supply partnerships and expanding market opportunities to provide solutions that deliver high performance, speed and efficiency. We sincerely believe that our Heterogeneous Integration journey will contribute immensely to the next generation of smart digital applications.Source: SPIL, 2020 VLSI Circuit Symposium

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