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Embracing a ‘People First’ Approach in Human Resource Management

At ASE, we center our focus on "People" and create a human-centric framework that revolves around improving the quality of employees’ work and daily lives. We listen to their needs; from food, healthcare, housing, transportation, education and entertainment, and tailor our programs to meet those needs as close as possible. As the largest and most advanced manufacturing site in the ASE group, the Kaohsiung campus is fully equipped with facilities including a health center, kindergarten and foreign worker hostel.During the past two pandemic years, the Kaohsiung team has maintained a high degree of vigilance and put in place preventive measures to protect employee health as well as mitigate any risk to the community. We tailor and adapt our policies as the pandemic evolves, ensuring business continuity and minimal disruption to the daily lives of our employees. In addition, for our 4,000 migrant employees, we provided comprehensive support and assistance that included vaccination against Covid19, dedicated transportation to/from work and counselling sessions. Our policy embraces compassion and empathy as we aim to provide a home away from home for these employees, and reduce their burden and stress while separated from their families and loved ones.The future of the semiconductor industry and demand for IC chips remain strong and steady. As we enter the era of smart manufacturing, ASE Kaohsiung is leading the OSAT industry in developing state-of-the-art smart factories that deliver the most advanced technologies and solutions to the market. ‘People’ are key to digital transformation and ASE has built a strong foundation in training and upskilling to equip employees for the smart future. At the same time, we continue to recognize the hard work and contributions of employees, and reward them with competitive salary adjustments and regular bonuses, among other incentives.ASE advocates a relationship with employees built on trust and partnership. We remain focused on providing the most comprehensive HR programs to take care of employees, ensuring a healthy, happy and energetic workplace. Together, we will create a stable and sustainable enterprise that results in the establishing of stronger ties amongst employees and the community.This May Day, we like to take the opportunity to appreciate each and every one of them for their resilience, unwavering commitment and contributions to the company. Happy Labor Day!

Sunny Li, VP ASEKH 4/29/2022 ESG

Enabling next-generation System Integration with scalable SiP solutions for Healthcare Applications

Semiconductor miniaturization and chip integration trends are driving greater industry focus on system-in-package (SiP) developments. SiP is a cost effective package integration technology that features higher performance and reduces time to market. These advantages allow chip companies to design electronic products that integrate more functions and develop new technology applications. Dr CP Hung, vice president, ASE Corporate R&D offers an insight on the application of SiP technology in healthcare electronics.Continuous Glucose MonitorA continuous glucose monitor (CGM) is a small wearable device that tracks blood sugar levels throughout the day and help detects trends and patterns. The data allows doctors and patients to better manage diabetic conditions. A CGM consists of a sensor, data transmitter and receiver, and the results are tracked via a monitor or a smartphone app.ASE’s SiP technology supports the integration of different microcontrollers (MCUs), application-specific integrated circuits (ASICs), antennas and sensors that control all the functions in a CGM, onto a single package structure. The packaging process offers miniaturization without compromising the performance of the device.In Vitro Diagnostics In vitro diagnostics (IVD) are tests performed on samples, such as mucus or blood, taken from the human body to help detect diseases or other conditions. The information obtained from analysis of such samples are used by health practitioners to monitor a patient’s overall health, and to treat or prevent diseases. A variety of IVD devices and systems are used by healthcare professionals in clinics, labs and hospitals, as well as by consumers at home.Complex IVD module designs are made possible with SiP technology processes that allow the integration of the bio-sensor chips and the microfluid receptacle through the use of customized molding techniques.Sensor ApplicationsWafer-level SiP technology is another packaging technique that applies through-silicon via (TSV) chip-scale package (CSP) processes to reduce the XY area size by 30% compared with traditional quad flat no-lead (QFN) packaging. At the same time, the electrical performance of the package structure is enhanced through lowering the resistance level by almost 80%.Sensor Hub A sensor hub is a microcontroller unit that integrates and processes data from various sensors. Through-silicon via (TSV) and chip-to-wafer (C2W) bonding are techniques used to design chips inside sensor hubs. Other methodology of chip design include placing ASIC and sensor components side-by-side, or placing a TSV die on top of another standard die.Wafer-level SiP technology can be applied in many types of sensor packages including 3D inertial, gas, temperature and humidity sensors. The data in the diagram shows that WL SiP package sizes can be reduced by between 25% to 77% compared with traditional packaging processes.ASE provides a complete suite of packaging and test services – from package design, functional simulation to testing, verification, volume production and final testing. ASE continues to provide industry-leading system-in-package integration solutions to help customers speed up product development.

Evelyn Lu 4/22/2022 Technology

AI is powering the future of Smart Factories

ASE is at the forefront of Industry 4.0 and innovating ahead of the curve with the use of AI in smart manufacturing. The use of robotics, autonomous machines and vehicles to create a safe, flexible, efficient and intelligent work environment is advancing our vision to becoming a world class service provider.We recently teamed up with the City of Kaohsiung to film this short video of dancing robotic arms exhibit at the 2022 Festival of Lights (Feb 1-28). The result is an amazing combination of creativity in visual arts with AI-powered technologies. What the human mind can conceive, can be achieved!To learn more about ASE’s Industry 4.0 and our milestones, please go to https://ase.aseglobal.com/en/solution/industry4point0

Jennifer Yuen 2/21/2022 Others

Unlocking More in Wearable Devices

The rapid development of smart wearable devices is driving improvements in sensor and packaging technology that offers unprecedented business opportunities for the semiconductor industry. System-in-Package (SiP), a packaging technique that enables highly integrated miniaturized systems through the integration of different sensors and chips with multiple functions (MCU, memory and more) within a small form factor, is fast becoming the preferred packaging solution for future wearable devices.SiP technology is designed to enable dense circuitry, which in turn allows miniaturization, lowers power consumption, improves radio frequency and maximizes functional capacity. Additional IC testing and testing of aged units further ensure chip performance and consistent quality. From smart watches, smart glasses to Bluetooth headsets, SiP integration technology is enabling chip designers to customize solutions easily. For example, more than 30 components can be integrated onto a single chip with a size of 4mmx8mm or 4.55mmx9mm, vastly reducing the product size and its overall weight by 1 gm or more.Watch MoreSiP Solutions for HearablesIn the designing of hearable devices, miniaturization is achieved through SiP packaging because it reduces the motherboard area and mitigates radio frequency and audio interference. Features like acoustic design and active noise control can be easily adjusted thereby, freeing up more space to optimize the acoustic cavity design to produce better sound quality and increase battery life. The addition of a built-in antenna using an AiP (Antenna-in Package) solution can further optimize the isolation between audio and radio frequency.ASE’s SiP solution provides several advantages to customers:Reduces inventory and material inspections, simplifying assembly and testing processes.Reduces assembly manpower and work processes.Provides customized solutions that meets product design and acoustic specifications.Reduces time-to-market and provides a cost competitive solution.The ASE SiP ToolboxASE offers customers a complete SiP solution covering:Module design and developmentSiP development board and antenna designPCBA software and hardware integration, development and debuggingVolume assembly and testing solutions

Evelyn Lu 10/12/2021 Technology

Premiering ASE Technology and Solutions at 2021 WSCE China

At this week's World Semiconductor Conference held in Nanjing, China, ASE, together with SPIL and USI, showcased the company's complete solution platform that encompasses its leadership in System-in-Package (SiP) and Advanced Packaging. ASE is a primary architect in Heterogeneous Integration which is helping to drive developments in HPC, IoT and automotive electronics.Unleashing the synergy of ASE, SPIL and USI to drive chip performance and solve chip design challengesChip First and Chip Last Fan-Out Packaging solution platform which allows the designing of high performance computing chips with high density2.5D/3D IC packaging solutions supporting high bandwidth and low latencyDesign and manufacturing experience in chiplet packaging technology at SPIL – the portfolio includes FO-MCM+EHS-FCBGA(Fan-Out Multi-Chip-Module + Exposed Heat Sink-Flip Chip BGA), HBW-POP(High Bandwidth Package-on-Package), FO-POP(Fan-Out Package-on-Package), ETS-SiP(Embedded Trace Substrate-System in Package), FO-SD(Fan Out-Single Die)USI’s proven miniaturization capabilities that support the wireless and mobile communication markets including LTE Cat.1 communication module, TWS Bluetooth audio module, wireless communication module, dual-core wireless microcontroller (MCU) equipped with Bluetooth®5, OpenThread and ZigBee®3.0. USI’s solutions are widely applied in devices with small footprints such as fitness watches and wearable products, TWS headsets, mobile devices, routers, industrial IoT, healthcare devices and tracking devicesEnabling a Smarter World We are accelerating a smarter world through our advanced packaging and module solutions.Complete Solutions for Smart Factories, Smart Cities and IoT-SiP (ASE, SPIL) + System-on-Modules (USI)Safety and Reliability in Smart Automotive. Wire bond, flip chip, WLCSP, SiP and discrete packaging portfolio (ASE, SPIL) + automotive power control modules (USI)ISE Labs China is our first engineering center in China that has received VDA6.3 and AECQ certification and mass production qualifications for automotive electronic chips.Smart Wearables. ASE’s TWS SiP modules enable more functions to be integrated onto a limited space. DockSiP and MicroSiP packaging solutions support miniaturization and ease of integration. Other solutions include integrated MEMS & Sensors, low-power antenna packaging and double-sided thin wireless communications.Playing a Leading Role through Innovation, Investment and CollaborationInvited to speak at the Innovation Summit, Dr. KK Kuo (VP, R&D ASE CHINA) provided his insights on the industry landscape and remarked, ‘The 5G+AI digital era and the evolution of Moore's Law has accelerated the demand for chip miniaturization, high performance and low power consuming chips that contribute to continuous breakthroughs in advanced packaging technology. Heterogeneous integration applications are on track to demonstrate explosive growth in the future, driven by rapid growth in high-performance computing (HPC), 5G, application processor engines (APC), automotive radars, radio frequency, audio, power management integrated circuits (PMIC) and many other applications. High-density packaging will increase in importance and advanced packaging and SiP will help drive the development for the next generation of semiconductor technologies. ASE Group will continue to play a leading role through innovation, prudent investments and industry collaboration.’

Evelyn Lu 6/10/2021 Technology

Developing water resilience strategies for a secure and sustainable future.

Taiwan, an island dotted with scenic mountains and lakes, is facing its worst drought in decades. Not a single typhoon (the heavy rains replenish the reservoirs) made landfall in Taiwan last year. The lack of rain this year is exacerbating the situation even further. The use of water to eliminate contamination of semiconductor chips during the manufacturing process has been intensive, and water shortage is posing a huge challenge to the industry.So, what has ASE done to mitigate the water crisis? Since 2015, ASE has built and operated its own Water Recycling Facility in Kaohsiung to process and recycle water to its own plants within the Nanzih Park, further reducing our dependence on tap water. The reduction in the use of tap water by ASE has enabled the city of Kaohsiung to deploy the water reserves for household, agriculture and other consumption. To learn more about ASE’s water recycling, please visit the page on water recycling.Today, only one-third of the water used in the Kaohsiung facilities is tap water, while two-thirds of it is recycled water. In May, our total accumulated water savings from the recycling facility has surpassed 20 million tons. While we are proud of this achievement, we will not rest on our laurels. The ASE management team has lifted the goalpost higher and established new water management KPIs for the company. We have drawn up plans to reduce our water usage, and increase investments to expand the water recycling facility so as to increase our ability to process, recycle and reuse as much water as possible. ASE strategy remains focused on balancing the demand and available resources.As a major industry player and one of the key contributors to Taiwan’s economy, we have stepped up and assumed greater responsibility on sustainability issues. We will embrace the latest technologies to create innovative educational programs that are aimed to improve engagement and raise awareness in water conservation to a wider and more diverse group of audiences. Recently, we have equipped the ASE Green Technology Education Center with VR capabilities that tap on a fast and high bandwidth 5G network. The VR showcase will enhance visitor experience and transform sustainability education in the digital age. To that end, the ASE Green Technology Education Center will continue to perform an important role in promoting public awareness on water and other sustainability issues.The survival of society, the environment and the economy depend heavily on water security and sustainability. Each drop of water is precious and we must all do our part to protect earth’s limited resources, and ensure a bright future for generations to come.About the ASE Water Recycling FacilityThe ASE Water Recycling Facility (also known as ASE K14) was established in January 2015 and is located at the Nanzih Technology Industrial Park, Kaohsiung. Phase 1 operations began in 2015 with a daily processing volume capacity of 20,000 tons and a recycling rate of 55%. When Phase 2 operations began in 2019, the recycling facility was able to receive and process wastewater from ASE’s manufacturing plants in NTIP Zone 2 in addition to those located in Zone 1. Its recycling rate was further improved to 70% and in May 2021, the company has surpassed 20 million tons of accumulated water savings, equivalent to the total water consumption of Kaohsiung residents in a month. By maximizing its own water resources, ASE was able to recycle every drop of water at least 3 times.

Jennifer Yuen 5/12/2021 ESG

Heterogeneous Integration Fuels the Future

Moore's Law has driven the semiconductor industry for decades, but in recent years, there has been deceleration in terms of performance and economic benefit. The exponential cost of silicon scaling has created an inflection point for the industry, and that is driving the development of More-Than-Moore technologies to augment device functionality and strengthen system performance. A Brief History of Semiconductor RoadmapsThe semiconductor industry comprises highly specialized yet closely interdependent companies that must stay on top of technology and market application trends to keep developments on track. As the industry grew, it became imperative by the 1990s that global semiconductor companies must work together to ensure progress was heading in the same direction. In 1991, semiconductor companies in the United States, under the auspices of the Semiconductor Industry Association (SIA), first established the National Technology Roadmap for Semiconductors or NTRS. By 1998, roadmapping efforts had expanded when companies from Japan, Europe, Korea, and Taiwan joined the NTRS effort, and together with SIA, they formed the International Technology Roadmap for Semiconductors (ITRS). SIA brought ITRS to a close in 2015, and that is when the Heterogeneous Integration Roadmap, or HIR, was initiated. Heterogeneous Integration Will Take Us ForwardHeterogeneous Integration refers to the integration of separately manufactured components into a higher-level assembly system-in-package (SiP) that in the aggregate provides enhanced functionality and improved operational characteristics. It is now the key technology direction going forward, driving the pace of advancement for greater intelligence and connectivity, higher bandwidth and performance, and lower latency and power per function, all at a more manageable cost. The Heterogeneous Integration Roadmap (HIR) is a roadmap to the future of electronics that identifies technology requirements and potential solutions. The primary objective is to stimulate pre-competitive collaboration among industry, academia, and government to accelerate progress. HIR is designed to provide long term continuity and a broad technology base. It is organized with sponsorship by three IEEE Technical Societies (Electronics Packaging Society, Electron Devices Society, and Photonics Society) together with SEMI and ASME Electronics and Photonics Packaging Division (EPPD). Technology takes a long time to develop and mature, and increasingly involves the collective knowledge from overlapping fields. It is therefore essential to set goals for the long-run and cover as many subjects and fields as possible, related to heterogeneous integration. As the industry enters the digital transformation and exascale computing era, massive compute with frequent access to data is required for high performance computing (HPC) applications. The increasing amount of data from all sectors is raising the issue of operational and storing cost of the data. The advent of artificial intelligence (AI) and machine learning (ML) requires large amounts of data to be processed and is driving an entirely new computing paradigm from edge computing to cloud to data centers. Traditional IC design trends are to pack more transistors on a monolithic die or system-on-chip (SoC) at each process node, resulting in difficult chip scaling for the integration of analog, logic, and memory circuits. The heterogeneous integration approach is die-partitioning or chiplets, which offers a compelling value proposition for yield improvement, IP reuse, performance, and cost optimization, as well as time-to-market reduction. Chiplet integration has the potential to allow the integration of disparate technologies from multiple suppliers to provide more flexible mix-and-match systems to accelerate performance and improve power efficiency without requiring the deployment of these technologies across an entire SoC simultaneously. Chiplet solutions start with internal designs within a system integrator. However, as IP interface standards are developed, the commercialization of chiplets in the market will proliferate. Heterogeneous Integration through chiplets will play a critical role for future HPC and AI/ML applications.ASE System-in-Package (SiP) Demonstrates Heterogeneous Integration. As a leading semiconductor packaging, test, and system service provider, ASE has heavily invested in both chip-level (SoC) package integration and system-level integration. The development of cutting-edge heterogeneous integration technologies addresses functional areas from silicon integration, power integration, optical integration to system integration that form the backbone of many electronic components, subsystems, and electronics products. ASE has developed and offers a wide portfolio of Si-level integration technology solutions, from low- to high-density chiplet integration including flip-chip multi-chip-module (FC-MCM), fanout chip-on-substrate (FOCoS), and 3D IC. The advanced FOCoS technology can provide short die-to-die connection and high interconnections (10,000s), redistribution layers (RDL) with 2µm line/space, and up to four layers for chip-first and chip-last packaging processes. It produces a lower-cost solution with improved electrical performance compared to a 2.5D Si interposer solution due to the elimination of Si through silicon via (TSV) processes and reduced insertion loss. ASE is evolving this advanced packaging platform to meet application demands for HPC and AI/ML applications. A Smarter, Healthier, More Efficient FutureLooking further into 2021 and beyond, key developments in packaging that create higher performance systems and utilize less power will be deployed. System performance will continue the pace of Moore’s Law era, albeit in a different way than with the previous total reliance on semiconductor chip lithography and SoC integration. There is tremendous optimism that innovations in the IC packaging industry will continue on a heterogeneous integration journey. Discovery, creativity, innovation, and very importantly, collaboration – will enable applications that make our world smarter, healthier, and infinitely more efficient. This article has been adapted from the blog article ‘The Future is Heterogeneous Integration’ by Dr Bill Chen. To read the full article, please click on https://www.3dincites.com/2021/01/the-future-is-heterogeneous-integration/

Patricia MacLeod 4/16/2021 Technology

Trends and Development in Heterogeneous Integration: Advancing the Smart Digital Age with System-in-Package and Chiplet Technologies

Heterogeneous integration (HI) is fast becoming a key driver of semiconductor development due to its ability to scale the number of individual chips onto a miniaturized system-in-package that enhances functionality, achieves higher efficiency, and even reduces power consumption. At the recently concluded SEMICON CHINA 2021 Advanced Packaging Forum, Dr KK Kuo (VP, R&D at ASE Jiangsu) delivered an insightful presentation on the trends and developments in Heterogeneous Integration and Fan-out Wafer Level Packaging.At present, HI technologies are enabled by: system-in-package (SiP) packaging that allows miniaturization and a higher level of integration; 2D/3D IC packaging that delivers higher bandwidth and lower latency; and Fan In/Fan Out Wafer Level Packaging (WLP) that achieves higher performance and higher density. To provide IC designers a robust automated design solution that addresses heterogeneous integration parameters, ASE collaborated with Deca Technologies and Siemens Digital Industries Software to launch the APDK™ (Adaptive Patterning® Design Kit). The APDK methodology provides IC designers a library of templates, extensive automation that guides the designer from initial layout to Adaptive Patterning simulation, to final design sign-off using Siemens’ Calibre software. ASE’s experience in volume production of highly integrated SiP including its M-series Fan-out WLP technology, demonstrates the company’s leadership in advancing device and system performance.Another trend in HI is the development of chiplets, a relatively inexpensive method that can quickly assemble independent IC chiplets (smaller and usually less expensive chips) through die-to-die interconnect, that when combined, accelerates the performance and power efficiency of the integrated package. An example of a chiplet architecture is the integration of CPU cores, memory ICs and 3D stacking technology to vastly improve bandwidth and interconnect quality. Chiplet designs are gaining popularity as the approach shortens the design leadtime and lowers the cost threshold – IC designers do not need to fabricate new chips using expensive nodes and fab processes. This methodology is now widely applied in designing high-end processors, FPGA and networking ICs.SPIL (a member of the ASE Technology Holding Co), has developed several fan-out packaging technologies to support chiplets including; Flip Chip Multi-Chip Module (FCMCM), 2.1D/2.5D/3D, Fan Out Multi-Chip Module (FOMCM), Fan-Out Embedded Bridge (FOEB) and Embedded Multi-die Interconnect Bridge (EMIB). The high acceptance rate of these process technologies are contributing to lower manufacturing costs and improving speed to market.Innovation in the packaging world is game changing, and the combined synergy from ASE, SPIL and USI is raising the company’s competitive edge and industry R&D standards. ASE is also building strong supply partnerships and expanding market opportunities to provide solutions that deliver high performance, speed and efficiency. We sincerely believe that our Heterogeneous Integration journey will contribute immensely to the next generation of smart digital applications.Source: SPIL, 2020 VLSI Circuit Symposium

Evelyn Lu 4/1/2021 Technology

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