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2.5D & 3D

As 5G, AI, and high-performance computing continue to make inroads into our world, there’s escalating demand for semiconductor devices that deliver enhanced performance, lower latency, increased bandwidth and power efficiency. 2.5D & 3D technologies deliver that, and more. ASE continues to push boundaries by innovating the 2.5D & 3D technologies that are becoming more and more crucial within the industry. ASE has well-established itself as a leader in 2.5D technology, having successfully delivered pioneering 2.5D solutions that helped bring advanced ASIC and HBM products to the market place. To continue this technology innovation momentum, ASE is introducing high density Fan Out technology for die stacking & multi-die solutions to achieve high bandwidth & high performance across the market landscape, addressing demand from high density data centers to consumer & mobile space.

ASE is one of the pioneers in 2.5D/3D packaging technology and has successfully introduced the mass production of the world's first 2.5D IC package equipped with High Bandwidth Memory (HBM). 2.5D refers to die stacking package using interposers to achieve the best performance of internet connectivity.

An Si interposer with TSV (Through Silicon Via) can be used as a platform to bridge the fine pitch capability gap between assembly substrate and integrated circuit board. It can help to keep the pad pitch scaling path without being limited by assembly substrate technology. In addition to the above advantage, integrating GPU, CPU and memory together with decoupling capacitor is also feasible by ASE 2.5D IC solution.

  • Higher level GPU and network server
  • FPGA
  • Game consoles
  • Single transfer by interposer
  • Data transfer distance reduced by 90%
  • 70% of the PCB footprint reduced by the HBM
  • Multifunction integration: ASIC + HBM
  • Low power consumption and high performance
  • Excellent heterogeneous integration technology


TSV-Interposer Integration

Si interposers with Through Silicon Vias (TSVs) have been many investigations into the manufacturing and characterization in ASE, the bonding methods for die to die attach, the handling of thin wafers, the novel assembly processes, and the testing methodologies and reliability of micro-bumps. With the high-density routing (L/S: 0.4/0.4um) and more than 200k micro bumps in one package, 2.5D technology enables the high bandwidth communication, homogeneous & heterogeneous chip integration and small form factor. 2.5D technology has already been a proven technology by many customers and IC vendors.

  • GPU (Visual Reality, VR)
  • Networking (Switch)
  • FPGA
  • HPC
  • Artificial Intelligence (AI)



Throughout the program, reliability was a significant focus. Package level reliability tests were carried out following JEDEC MSL pre-conditioning, Temperature Cycle Test (TCT), Highly Accelerated Temperature and Humidity Stress Test (HAST) and High Temperature Storage Test (HTST). Board-level reliability tests, including TCT, vibration test, mechanical shock test and monotonic bend test were designed, performed and assessed. Electrostatic discharge (ESD) control was confirmed for the new assembly and handling flows. Power cycling (PwrCyc) and TSV stress migration (SM) were employed to guarantee the new physical structure of the interposer and electro-migration (EM) was verified for the new interfaces.