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Flip Chip

Flip chip derived its name from the method of flipping over the chip to connect with the substrate or leadframe. Unlike conventional interconnection through wire bonding, flip chip uses solder or gold bumps. Therefore, the I/O pads can be distributed all over the surface of the chip and not only on the peripheral region. The chip size can be shrunk and the circuit path, optimized. Another advantage of flip chip is the absence of bonding wire reducing signal inductance.
An essential process for flip chip packaging is wafer bumping. Wafer bumping is an advanced packaging technique where ‘bumps’ or ‘balls’ made of solder are formed on the wafers before being diced into individual chips. ASE has invested significantly in the research and development as well as in equipment for wafer bumping. It has the capacity to bump 6-inch, 8-inch and 12-inch wafers.

Flip chip technology is gaining popularity due to

  • Shorter assembly cycle time
    All the bonding for flip chip packages is completed in one process.
  • Higher signal density & smaller die size
    Area array pad layout increases I/O density. Also, based on the same number of I/Os, the size of the die can be significantly shrunk.
  • Good electrical performance
    Shorter path between die and substrate improves the electrical performance.
  • Direct thermal dissipation path
    External heat sink can be directly added to the chip to remove the heat.
  • Lower packaging profile
    Absence of wire and molding allows flip chip packages to feature lower profiles.

Flip Chip in ASE

ASE offers several BGA packages using flip chip technology. There are:
I/O Package Size (mm) Substate Ball Pitch (mm)
FCCSP 16 ~ 200 4x4 ~ 14.0x22.0 2/4 Layer Laminate 0.5 ~ 1.00
Ceramic FCBGA/PGA < 1556 27x27 ~ 49.5x49.5 Ceramic 0.8 ~ 1.27
FCBGA 100 ~ 1521 27x27 ~ 40.0x40.0 2/4 Laminate,
4-8 Layer Build-up
HFCBGA 256 ~ 2401 12x12 ~ 52.5x52.5 4-12 Layer Build-up 1.0/1.27

Applications include RFICs and memory ICs. ASE provides packaging service for any customer-designed size at ball pitches ranging from 0.5 to 1.0mm, and number of I/Os from 16 to 200. The types of encapsulation are underfill and overmold.

FCCSP (Flip Chip Chip Scale Package) offers chip scale capacity for I/Os around 200 or less. FCCSP provides better protection for chip and better solder joint reliability compared with Direct Chip Attach (DCA) or Chip on Board (COB). FCCSP is more superior to Known Good Die (KGD) in low-cost test and burn-in, and performs comparable electrical function with KGD. FCCSP features thin and small profile, and lightweight packages.

Ceramic substrate offers better moisture resistance, electrical insulating property and higher thermal conductivity than organic substrate. High Pb solder ball with eutectic solder paste improves board level reliability performance of ceramic packages.
High Performance FCBGA (HFCBGA)

These two packages cater to I/Os of 100 to over 1500 with BT laminate or sophisticated multi-layer build-up substrates. HFCBGA is thermally enhanced through mounting a metal heat sink to the rear side of the chip and the substrate. This method can effectively remove the heat and improve the thermal performance.


The thickness and the available ball count of flip chip packages are mostly customized. ASE provides several options for enhancing the performance of flip chip packages. They are:

Overall molding (for FCCSP)
The molding is used to protect the chip, substitute underfill for lower cost and improve the thermal performance and 2nd level reliability.

Heat spreader (for FCBGA)
The heat spreader provides direct heat conduction by adhering to the rear side of the silicon chip. This method provides 6~8W of thermal dissipation under natural convection.