Chiplet integration* in high performance computing (HPC) applications is high on the agenda these days, with escalating demand for reliable advanced packaging technologies to achieve critical interconnection as efficiently as possible. At ASE, our high density FOCoS solutions offer that, and much more.
What is Fan-Out Chip on Substrate (FOCoS)?
FOCoS is a fan-out package flip-chip mounted on a high pin count ball grid array (BGA) substrate. The fan-out package has a re-distribution layer (RDL) that allows the construction of shorter die-to-die (D2D) interconnections between multiple chips. The fan-out package is treated as if it was a single die and then flip-chip mounted onto the BGA substrate.
ASE FOCoS Package Offerings
We offer a silicon bridge technology for implementing chiplet integration called FOCoS-B (Bridge), which utilizes tiny silicon pieces with routing layers as in-package interconnect between chiplets, e.g, graphics computing chips (GPU) and high bandwidth memory (HBM). The silicon bridges are embedded in the fan-out RDL layer as detailed below.
FOCoS-B is positioned as an alternative to 2.5D packages using silicon interposers. Like 2.5D, silicon bridges provide ultra-fine pitch interconnection in packages, which can address the memory bandwidth bottleneck challenges in systems. Compared with 2.5D, the advantages of FOCoS-B is that we only use silicon pieces in the areas where we are trying to connect two chiplets together.
There are two other types of fan-out chip on substrate (FOCoS) solutions: chips first (CF) and chips last (CL) as detailed below.
FOCoS-CF (Chip First)
This FOCoS-CF test vehicle consists of two ASIC chiplets facing down directly connecting with RDL through the Cu vias and no micro-bumps between the Si dies and fanout RDL (L/S 2/2 um).
FOCoS-CL (Chip Last)
The FOCoS-CL test vehicle is built up by three chiplets (1 ASIC die and 2 HBMs) in a side-by-side configuration. The ASIC die and 2 HBMs are connected through RDL (L/S 2/2 um) and Cu micro-bumps.
The FOCoS-B test vehicle consists of 2 chiplets (1 ASIC die and 1 HBMs). The Si bridge die (L/S 0.6/0.6 um) are embedded in the fan-out RDL layer (L/S 10/10 um) for making the connection between ASIC and HBM.