Fan Out Packaging
With the packaging done on singulated die formed into a reconstituted molded wafer, Fan Out packaging enables multi-die packages, through partitioning with different nodes and functionality. Initially Fan Out was used primarily for smaller, lower I/O count packages, until ASE introduced a very high-density Fan Out alternative to 2.5D Interposer packages, Fan Out on Substrate (FOCoS), a hybrid Fan Out/FCBGA package. Today, Fan Out is in high volume applications for a wide diversity of products, including PMICs, RF packages, Baseband processors, and high-end networking systems.
Key attributes include:
- arallel Manufacturing Process in Wafer Form
- Smallest Package in X, Y and Z
- Excellent Mechanical, Electrical, and Thermal Performance
(I) Chip-First, the chip is buried in the substrate material firstly and followed by RDL (Redistribution Layer) forming processes. Chip-First has substrate-like processes and fabricates larger pitch e.g. 20um, which provides a lower cost solution. Thus, its application is suitable for low I/Os.
(II) Chip-Last, chips are not integrated into the packaging processes until the circuits on the chip carrier are pre-formed. The Chip-Last process is known with less KGD yield concern compared with the Chip-First one. Chip-Last has better electrical performance, implies the package accommodated more I/Os, and possesses more ultra-fine pitch e.g. 2um and small through-via capabilities.
ASE offers both Chip-First and Chip-Last Fan Out packaging as shown below: