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Fan Out Packaging

With the packaging done on singulated die formed into a reconstituted molded wafer, Fan Out packaging enables multi-die packages, through partitioning with different nodes and functionality. Initially Fan Out was used primarily for smaller, lower I/O count packages, until ASE introduced a very high-density Fan Out alternative to 2.5D Interposer packages, Fan Out on Substrate (FOCoS), a hybrid Fan Out/FCBGA package. Today, Fan Out is in high volume applications for a wide diversity of products, including PMICs, RF packages, Baseband processors, and high-end networking systems.

Key attributes include:

  • arallel Manufacturing Process in Wafer Form
  • Smallest Package in X, Y and Z
  • Excellent Mechanical, Electrical, and Thermal Performance
Fan Out packaging can be done either chip first or chip last, with both options resulting in much higher density interconnect and improved cost efficiency.

(I) Chip-First, the chip is buried in the substrate material firstly and followed by RDL (Redistribution Layer) forming processes. Chip-First has substrate-like processes and fabricates larger pitch e.g. 20um, which provides a lower cost solution. Thus, its application is suitable for low I/Os.

(II) Chip-Last, chips are not integrated into the packaging processes until the circuits on the chip carrier are pre-formed. The Chip-Last process is known with less KGD yield concern compared with the Chip-First one. Chip-Last has better electrical performance, implies the package accommodated more I/Os, and possesses more ultra-fine pitch e.g. 2um and small through-via capabilities.

ASE offers both Chip-First and Chip-Last Fan Out packaging as shown below:

aWLP

Chip-First, chip embedded in mold compound, fan-out by wafer-level RDL

a-EASI

Chip-First, chip embedded in organic dielectric, fan-out by substrate-level RDL

Laminated FCCSP

Chip-Last, chip embedded in organic dielectric, fan-out by flip chip substrate


Panel Level Platform Fan Out Package

Chip-First, chip embedded in mold compound, fan-out by panel-level RDL
Size: 600x600mm



Application
Features
  • FPGA, CPU/GPU
  • Power Management IC Module
  • Baseband, WiFi Devices, RF Devices
  • Transducers
  • Networking, Servers
  • Mobile Devices, Consumer
Item Benefit Process I/O Characteristic Interposer
Chip-First Short cycle time Substrate firstly and followed by RDL processes Lower I/Os No need
Chip-Last Less KGD yield concern Chip not integrated into RDL processes More I/Os No need

Capabilities

Item Platform Package Size RDL Number RDL Pitch (min.) Direct Opening (min.)
Chip-First Wafer Based 5x5mm2 - 55x55mm2 < 3 < 20um < 20um
Chip-Last Wafer or Panel Based 12x12mm2 - 60x60mm2 < 3 < 2um < 10um

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