Wafer Level Packaging

To service the fast growing market within PDA and cell phone, this smaller chip size is essential. In 2001, ASE licensed Ultra CSP® from Kulicke & Soffa's Flip Chip Division. ASE also provided several enhanced structures called "aCSP™" by polyimide, PBO, or thicker Cu RDL to meet various customer demands. aCSP™ is a wafer level CSP package that can be Direct Chip Attached to the PCB board without any interposer. Also, aCSP™ provides the shortest electrical path from Al pad to PCB board to enhance the electrical performance. It has been broadly used in portable devices in passives, analog and logic applications, and is extending to RF applications.

Product Offering

• aCSP: Through ball drop process
• BWLCSP: Through ball printing/plating process

Advanced Technology under Development

• Wafer technology: Qualification for 90 and 65nm wafer
• Ball pitch: 300um
• Ball size: 150um ball drop
• Grinding: Die thickness 200um
• Plated RDL line/width: 10/10um; 6/6um
• Plated RDL thickness: >=7um
• Sawing: Laser sawing

ASE Wafer Level Integrated Passive Device (WL IPD) is a glass based wafer level process, well developed for today's most advanced RF communication solutions. It is with custom design, high performance and small form factor, fully compatible with current assembly process in QFN, BGA/LGA, Flip Chip packages, and in WLCSP. AIC (above IC) process is also available.

Reliability

ASE offers total turn-key solution from IPD design/simulation to process, package, and final test completed solution at one single stop. Fully characterized and well established design library for any design requirement. Production since 2011, and has shipped over 200 million units.