ASE has introduced VIPack™, an advanced packaging platform designed to enable vertically integrated package solutions. VIPack™ represents ASE’s next generation of 3D heterogeneous integration architecture that extends design rules and achieves ultra-high density and performance. The platform leverages advanced redistribution layer (RDL) processes, embedded integration, and 2.5D and 3D technologies to help customers achieve unprecedented innovation when integrating multiple chips within a single package.
As our world navigates the data centric era, the semiconductor market is growing exponentially, with the growth behind the data coming from devices used across Artificial Intelligence (AI), Machine Learning (ML), 5G Communications, High Performance Computing (HPC), Internet-of-Things (IoT), and Automotive applications. Demand for innovative package and IC co-design, cutting-edge wafer level fabrication processes, sophisticated packaging technologies, and comprehensive product and testing solutions has never been greater. The role of packaging has become increasingly critical, as applications call for solutions to enable higher performance, greater functionality, and improved power, while meeting stringent cost parameters. The rising adoption of chiplet-based co-designs is further fueling demand for multi-chip integration into a single package. The launch of VIPack™ firmly establishes a collaborative platform for exceptional interconnect solutions where 3D heterogeneous integration has become critical.
ASE’s VIPack™ is comprised of six core packaging technology pillars supported by a comprehensive and integrated co-design ecosystem: