Press Room

New San Jose Facility Houses Reliability and Qualification Processes, Fremont Site Broadens Focus on Test Functions

FREMONT, Calif. – July 11, 2024 – ISE Labs, Inc., a leading provider of semiconductor engineering services, today announced it is broadening customer access to its world-class capabilities with the opening of a second U.S. facility, located in San Jose, Calif. Together, the Fremont and San Jose sites will double ISE’s available R&D lab and business space, reinforcing the company’s commitment to Silicon Valley while expanding its North American footprint and helping to strengthen the U.S. semiconductor supply chain. The grand opening ceremony for the new facility at 2201 Qume Drive in San Jose is set for tomorrow at 11:00 a.m. PDT.

ISE Labs purchased the building in late 2023 and has built it out specifically to accommodate the engineering needs of its North American customers, many of whom are working on solutions for emerging semiconductor applications, such as artificial intelligence/machine learning (AI/ML), advanced driver assistance systems (ADAS), and high-performance computing (HPC), to name a few. In addition to shifting some team members between facilities, ISE Labs is seeking a number of highly skilled engineers and technicians for the new site.

According to Kenneth Hsiang, Chief Executive Officer, ISE Labs, “As semiconductor manufacturing supply chain reshoring continues to escalate, demand for our proven engineering expertise is growing in parallel. Expanding our operations by adding a second facility is vital to support our growing customers, who are onsite daily due to the collaborative nature of our work. Ease of access in the South Bay was a key consideration in selecting our new site.”

The San Jose facility will primarily house qualification and reliability process, including environmental, mechanical, electrostatic discharge (ESD), failure analysis, and burn-in. ISE Labs’ high-power burn-in solutions – vital to detecting early failures in a semiconductor device – are among the best and highest-performing in the industry. The Fremont site will expand its already robust set of test functions, including automated test equipment (ATE) test program development, test hardware design, device characterization, wafer probing, and engineering, pre-production and final test, and system-level test.

“We are firmly committed to our investment in Silicon Valley. It both contributes to the region’s revitalizing its position in the semiconductor industry and supports U.S. manufacturers more broadly. Adding this new high-end facility to our existing local footprint is an important step,” said Dr. Tien Wu, Chief Executive Officer, ASE, Inc. “Our ISE Labs division – the largest semiconductor testing service provider in North America – is essential to advancing ASE’s role in driving the development of the world’s most innovative electronics.”

The grand opening event will feature remarks from San Jose Mayor Matt Mahan; Poonum Patel, Deputy Director of Business Development, Governor’s Office of Business and Economic Development (GO-Biz); and other dignitaries, followed by a ribbon-cutting. The agenda will then segue into two brief, dynamic Q&A panel sessions that will further underscore the significance of the new facility to the companies, the region, and the semiconductor industry supply chain. A networking luncheon and facility tours will complete the event.

About ISE Labs, Inc.

Established in 1983, ISE Labs has a wealth of experience and expertise to serve the semiconductor community. The company’s broad offering of engineering services and products includes test engineering support, production test services, test program development, test interface and reliability test hardware, ESD, burn-in, environmental testing, mechanical testing, and failure analysis.

ISE Labs is a subsidiary of ASE, Inc. The world leader in advanced semiconductor assembly and test services, ASE offers a wide portfolio of technology and solutions for IC test program design, front-end engineering test, wafer probe, wafer bump, substrate design and supply, wafer level packaging, flip chip, system-in-package, and other manufacturing services.