IC packaging technologies in the past decade developed rapidly for various devices, such as FO-WLP (Fan-Out Wafer Level Package), SiP (System in Package), 3D IC, 2.5D TSV (Through Silicon Via) interposer and so on. Among the various technologies, FO-WLPs benefit in miniaturization, total system cost reduced, and heterogeneous integration. FO-WLPs are in wide range of applications, e.g. FPGA (Field Programmable Gate Array), GPU (Graphics Processing Unit), networking, RF/WiFi (Radio Frequency/Wireless Fidelity) module, PA (Power Amplifier) module, etc. FO-WLPs have two categories: one is called Chip-First and another is Chip-Last.
(I) Chip-First, the chip is buried in the substrate material firstly and followed by RDL (Redistribution Layer) forming processes. Chip-First has substrate-like processes and fabricates larger pitch e.g. 20um, which provides a lower cost solution. Thus, its application is suitable for low I/Os.
(II) Chip-Last, chips are not integrated into the packaging processes until the circuits on the chip carrier are pre-formed. The Chip-Last process is known with less KGD yield concern compared with the Chip-First one. Chip-Last has better electrical performance, implies the package accommodated more I/Os, and possesses more ultra-fine pitch e.g. 2um and small through-via capabilities.
ASE currently FO-WLPs have achieved by Chip-First involving dies embedding in a laminate or organic wafer with face up/face down followed by thin through-via and RDL interconnections. FO-WLPs also means that the interconnections need to be 3-8X smaller in dimensions as compared to existing flip-chip technologies (70um-80um) in order to achieve ultra-fine pitch interconnections. ASE offers both Chip-First and Chip-Last packaging solutions. There are several different package groups belong to this embedded-chip family: