Press Room

TAIPEI, Taiwan, July 8th, 2003 – Advanced Semiconductor Engineering Incorporated (ASE, TAIEX: 2311, NYSE: ASX), one of the world’s largest semiconductor packaging and testing companies, announced today that it has launched volume production of chip packages using Polymer Collar WLP™ – a wafer level process licensed from Kulicke & Soffa Industries Inc (K&S), which enables 30%~50% increase in solder fatigue life. The company has ramped up wafer level package production capacity of up to 10 million units per month.

Polymer Collar packaging is an enhancement of K&S’s Ultra CSP™ wafer-level package technology which ASE has previously licensed in January of 2001. “Flip Chip customers around the world are starting to see the benefits of polymer collar and we are pleased that ASE has moved to this new enabling technology, ” stated Jack Belani, Vice President, Marketing at Kulicke & Soffa. The technology combines an epoxy-based carrier with flux agents to form a polymer structure, or “collar, ” around the solder ball neck – or chip-side solder joint, increasing solder fatigue performance. During manufacturing, addition of the Polymer Collar replaces the traditional fluxing step, resulting in a simplified manufacturing solution. The Polymer Collar WLP significantly improves the solder joint reliability and increases the application space by enabling larger area arrays. Thermal cycling test on Polymer Collar Ultra CSP packages demonstrated greater than 30%~50% increase in solder joint life compared to a standard Ultra CSP.

“Conventional wafer level packaging limits package sizes and the solder joints are susceptible to thermal fatigue. To counter these challenges, ASE has evaluated various processes and had go od success in the application of Polymer Collar WLP, ” said J.J. Lee, President of Research and Development, ASE Group. “With ASE’s Polymer Collar WLP manufacturing capability, our customers can now use larger dies and higher I/O in wafer level packaging for their end products and meet improved reliability requirements. As a result, customers designing for chip scale package technologies such as TSOP, QFP and QFN may consider migrating to wafer level packaging as another option.”

“The simplicity of wafer level packaging has led to significantly lower manufacturing costs, while its small form factor has made it most suitable for mobile and portable electronic products, ” added J.J. Lee. “Adding the benefits of Polymer Collar WLP has effectively broadened the application of wafer level packaging to more electronic products such as cellular phones, PDAs, digital cameras and computer components.”

Editor’s note: Polymer Collar WLP™ and Ultra CSP® are trademarks of Kulicke & Soffa Industries Inc.