Fabrication process of Fan-Out Chip on Substrate (FOCoS)
The FOCoS fabrication process can be simply divided into three phases: wafer level reconstruction, re-distribution layer and package level flip-chip assembly. FOCoS fabrication methods include chip first and chip last processes as illustrated below:
Chip-first FOCoS process
Chip-last FOCoS process
Benefits of Fan-Out Chip on Substrate (FOCoS)
FOCoS eliminates the need for an interposer which helps to reduce the package cost. FOCoS also has less insertion loss, better impedance control and lower warpage, thereby offering better electrical performance.
Key advantages of applying Fan-Out Chip on Substrate (FOCoS):
- Lower cost (w/o TSV, microbump and thinner substrate)
- Thinner package
- Good electrical performance (shorter D2D connect)
- High I/O counts (> 1000)
- Time to market with existing Fan-Out/Flip Chip techniques
Fan-Out Chip on Substrate (FOCoS) Applications
FOCoS is ideal for large package sizes and packages with high I/O density (> 1000 I/Os) that are designed for networking and server applications. The chip-last version of FOCoS can be used to package application-specific integrated circuits (ASICs) and high-bandwidth memories (HBM).
FOCoS Assembly Design Kit (ADK)
ASE, in collaboration with Siemens Digital Industries Software OSAT Alliance Program*, has developed a fully validated ADK that helps customers create and evaluate complex FOCOS packages in an easy-to-use, data-robust graphical environment prior to and during physical design implementation. By adopting the Siemens Xpedition Substrate Integrator and Calibre® 3DSTACK technologies, and through integration with the current ASE design flow, this ADK can significantly reduce FOCoS package planning and verification cycle times by about 30 to 50 percent in each design iteration.
The comprehensive design flow enables us to quickly and easily co-design FOCoS packages with our customers and close any physical verification issues.