This is posts with tag name "AI"

post

Advanced Packaging from FOWLP to FOPLP Development of FanOut Chip Last in 300 mm Panel

As the demand for high-performance computing (HPC) continues to rise, processor designs are evolving towards chiplet integration and ASIC-HBM architectures, leveraging high-density interconnection technologies. While wafer-level fan-out packaging (FOWLP) has become a widely adopted solution, it faces challenges such as warpage control, complex processes, and carrier utilization limitations. To address… Read More

post

Technology Enhancements on FOCoS-Bridge for Emerging Trends in HPC and AI

In the rapidly evolving fields of High-Performance Computing (HPC) and Artificial Intelligence (AI), the demand for higher bandwidth, greater I/O density, and improved thermal dissipation is increasing. To meet these challenges, we are proud to introduce “FOCoS-Bridge with TSV” as an advancement to ASE’s VIPack™ FOCoS-Bridge technology. This enhancement integrates a bridge… Read More

post

ECTC 2025 Part Two

We announced Fan-Out Chip-on-Substrate-Bridge (FOCoS-Bridge) with Through Silicon Via (TSV), a significant packaging advancement to help propel technology enablement for AI and its pervasive impact on global life. It’s part of the continued evolution of ASE’s VIPack, our scalable advanced packaging platform that continues to expand in alignment… Read More

post

ECTC 2025 Part One

What an incredible week we had at ECTC2025, with its record-smashing attendance, powerful presentations, insightful conversations, and consequential networking. Huge thanks to everyone who helped make ASE’s presence at ECTC our best yet! A special shout-out to Florian Herrault, Przemek Gromala, Alan Huffman,… Read More

post

SEMICON SEA 2025

From insightful and riveting keynote presentations by Dr. Tien Wu and Ingu Yin Chang to engaging conversations at our ᴡᴏʀᴋꜰᴏʀᴄᴇ ᴅᴇᴠᴇʟᴏᴘᴍᴇɴᴛ ʙᴏᴏᴛʜ,  SEMICON SEA 2025 was a powerful showcase of collaboration, innovation, and talent development in shaping the semiconductor future. We’ve compiled a short video clip that captured memorable moments of the 3-day event.Advanced Packaging technology… Read More

post

Integrated Design Ecosystem™ for Chiplets and Heterogeneous Integration in Advanced Packaging Technology

As the demand for high-performance computing (HPC) continues to grow, chiplets and heterogeneous integration have emerged as key solutions due to their significant advantages in improving yield, reusing IP, enhancing performance, and optimizing costs. The integration of chiplets, particularly for AI applications, necessitates a greater number of connections than traditional… Read More

post

AI and Semiconductor in Reciprocity

In today’s rapidly advancing technological era, AI has become a powerful catalyst for innovation and progress. Advanced semiconductor packaging plays a crucial role in supporting AI development, while AI applications create new semiconductor demands and drives the development of semiconductor technologies, with both complementing each other. Semiconductor Packaging: The Bridge… Read More

post

Advanced Packaging Evolution: Chiplet and Silicon Photonics-CPO

As we enter the AI era, the demand for enhanced connectivity in cloud services and AI computing continues to surge. With Moore’s Law slowing down, the increasing data rate requirements are surpassing the advancements of any single semiconductor technology. This shift underscores the importance of heterogeneous integration (HI) as… Read More

post

Signal Integrity Analysis of UCIe Channel in FOCoS Advanced Package

In chiplet integration applications, various chips from different vendors can be integrated into one package structure using the Universal Chiplet Interconnect Express (UCIe) standard. Fan-Out Chip on Substrate (FOCoS) is a promising advanced package that can achieve high channel density and high bandwidth. However, crosstalk in high-speed signals is a… Read More