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Welcome to VIPack™

There are still many unknowns as we continue through challenging global times. However, it is inspiring to see such game-changing innovation within the semiconductor industry, ultimately enabling applications that are literally changing lives, from health to transportation, from robotics to AI, from edge to cloud, from 5G to beyond. Collectively, we are helping to improve lifestyles and efficiencies by creating a smarter and more sustainable world for generations to come.ASE is blazing new trails in device miniaturization and integration, and ongoing innovation means we are delivering advanced packaging and System-in-Package solutions to meet growth momentum across a broad range of end markets, such as automotive, 5G, AI, IoT, high performance computing, and more.In recent times, we have presented many solutions for SiP. Today we present ViP, or VIPack™, an advanced packaging platform designed to enable vertically integrated package solutions. VIPack™ represents ASE’s next generation of 3D heterogeneous integration architecture that extends design rules and achieves ultra-high density and performance. The platform leverages advanced redistribution layer (RDL) processes, embedded integration, and 2.5D and 3D technologies to help customers achieve unprecedented innovation when integrating multiple chips within a single package. To summarize, the VIPack™ platform enables heterogeneous integration through multi stack RDL layered package structures.ASE’s VIPack™ addresses the following device challenges: insertion loss, integration challenges, clock/speed, height, power delivery, and dense IO, all very critical area, and it is specifically geared towards mobile, high-performance computing, networking, and RF.The VIPack™ platform comprises six core packaging technology pillars supported by a comprehensive and integrated design ecosystem. These technology pillars include ASE’s high density RDL based FOPoP, FOCoS, FOCoS-Bridge, and FOSiP as well as TSV based 2.5D/3D IC and Co-Packaged Optics processing capabilities. It provides vast capabilities necessary to enable the next generation highly integrated silicon packaging solutions required to optimize clock speed, bandwidth, power delivery and the ability to optimize co-design time, product development and time to market. Such includes Double Sided RDL/Fan-Out, RDL Integrated Passives, Ultra Dense Routing, Advanced Materials, and DTC Integration.VIPack™ touches most market segments and has many sub-package platforms where high performance is needed or alternative solutions to ABF/Substrate based routing. It will extend most advanced package technology roadmaps and there are significant cost and performance advantages when considering VIPack™.Ultimately, today’s advanced silicon nodes are pushing the limits of power delivery where noise and performance are critical while managing overall power. VIPack™ enables a suite of packaging solutions, addressing multiple market segments, that are targeted to provide solutions to these challenges and enable an extension to advanced packaging roadmaps.We welcome you to discuss VIPack™ with us!For more about VIPack™, please visit ase.aseglobal.com/en/vipack

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2.5D vs Fan-out Chip on Substrate

The demand for high bandwidth and high-performance applications such as networking, AI computing and GPU IC chips are driving innovative developments in advanced IC packaging. Heterogeneous integration enables the integration of multiple chips using fine line/space interconnect packaging technology.Heterogeneous integration packaging solutions offered in the market today include, through silicon via (TSV) interposer technology:2.5D IC packagingand re-distribution layer (RDL) fan-out process better known as fan-out chip on substrate package (FOCoS).FOCoS fabrication methods include chip first and chip last processes. We have utilized FEA simulations to examine the warpage, ELK layer crack risk, interconnection/RDL trace broken risk, and board level solder joint reliability of three package types: 2.5D IC, chip-first FOCoS and chip-last FOCoS. The validity of the simulation model is confirmed by comparing the numerical results for the warpage and thermal mechanical deformation of chip-last FOCoS with the experimental observations by advanced Metrology Analyzer (aMA) system. Further CFD simulations are then performed to investigate the heat dissipation performance of the three package types.We have investigated the warpage and in-plane thermal deformation of packages at various environment temperatures. Three-dimensional numerical models have been developed to compare the mechanical and thermal performance. The warpage and inplane thermal deformation of the FEM model has been validated with the measurement result. Having validated the FEM model, this study applied the FEA investigations to package types' comparison and examine the influence of the chip-last FOCoS wafer level underfill material properties on the D2D area interconnection copper trace reliability.The results from the numerical simulation are as follows:The warpage of the two FOCoS package types are lower than 2.5D IC due to smaller CTE mismatch between combo die and stack-up substrate. Besides, the chip-last FOCoS has the lowest warpage quantity with the contribution of wafer level underfill.The ELK stresses of FOCoS for both chip-first and chip-last are lower than 2.5D package, because RDL/PI layers are the effective buffering to reduce ELK layer stress.The solder ball with maximum CSED occurs on the outermost solder joint located on the package edge of the solder joint top side, i.e. substrate side, surface. All these three packages have insignificant difference on CSED. It means that the board level TCT performance is similar because the equivalent CTE of all the package types are similar.The interconnection copper trace stress of 2.5D package has lower stress than others due to smaller localized CTE mismatch to reduce copper trace stress.The wafer level underfill type D with higher Tg and lower CTE has lowest stress, which could enhance copper trace reliability performance.2.5D IC, chip-first FOCoS and chip-last FOCoS have similar thermal performance and all of them are good enough for high power applications.More information can be found in theECTC articleentitled "A comparative study of 2.5D and fan-out chip on substrate: Chip first and chip last".

Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-out Chip Last Packages

In recent years, Fan-Out (FO) packages have become widely used in handheld, mobile consumer and internet of things (IoT) devices. FO packaging allows greater I/O density as well as the ability to pack multiple components in the same package compared to conventional wafer level chip scale package (WLCSP). Several types of FO packaging are offered in the market today, for example; embedded wafer level BGA (eWLB), M-Series™ as well as a flip chip based structure referred to as Fan-out Chip-Last Package (FOCLP).We have investigated the mechanical and thermal performance of these FO packages. Finite element analyses were carried out to examine mechanical performance metrics, including warpage, stress in the extreme low-k (ELK) interconnect and board level solder joint reliability. Thermal simulations were completed to compare the thermal dissipation differences among the FO package types. We also applied the optical profile measurement facility advanced metrology analyzer (aMA) to investigate the correlation between in plane strain and out-of plan warpage of fan-out packages at various environment temperatures. A three-dimensional computational model has been developed to compare mechanical and thermal performance of different fan-out package types.The aMA measurement results have shown that the warpage quantity of M-Series™ structure is lower than eWLB. Besides, the dimension change of eWLB is higher than M-Series™. The performance of the fan-out packages FE model has been verified by comparing the simulation results for the package in-plan dimension change with those obtained experimentally.In addition, the numerical simulation results show that:The maximum warpage of all types are less than 25um. FOCLP has higher warpage due to high CTE mismatch between thin coreless substrate and compound. Besides, the M-Series™ has lower warpage quantity because backside coating film help to balance CTE mismatch to reduce warpage.The ELK stress of FOCLP and M-Series™ are similar and lower than other package types. This is the result of the molding compound RDL above the copper pillars acting as a stress buffer.The solder ball with maximum Creep strain energy density (CSED) occurs on the outermost solder joint located on package edge at theUBM edge. eWLB and M-Series™ packages have similar CSED, while FOCLP has lowest CSEDvalue. This is due to less CTE mismatch between the PCB and the FOCLP package.The different types of fan-out packages have similar thermal performance and, overall, dissipate heat better than WLCSP.More information can be found in theECTC articleentitled "Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-out Chip Last Packages".

Business un-usual: Resilience in the face of a pandemic.

Early 2020 was certainly unforgettable for many of us in Asia. Around that time, the COVID-19 (known then as the Wuhan virus, or simply coronavirus) caseload was already spiraling out of control in Wuhan, the city where the virus was first detected at a seafood market. Wuhan, the epicenter of the outbreak, was locked down by the Chinese government on January 23rd. Our company’s management mobile group chat was abuzz non-stop about the situation in China, especially in and around our facilities. It was the Spring break where many Chinese traditionally return to their hometowns and many businesses remain shut for the celebration. No one knew exactly how widespread the disease had affected populations beyond Wuhan, but somehow we knew that we have to plan for the worst.The ASE crisis management mechanism was immediately triggered. We established a special task force and developed an advanced data management system to coordinate COVID-19 measures across all ASE locations. Each factory had set up a ‘command room’ to deploy the company’s business continuity plan across the entire organization. Appointed personnel were actively communicating with local authorities to keep lockstep with the situation, as well as to implement measures based on the governments’ advisories. During that time, the situation in China was especially intense, as the disease continues to spread to other cities.Our top priority was to ensure the safety of our employees. With this in mind, our procurement teams became very busy scouting for essential personal protective equipment, especially surgical masks. Masks were suddenly in high demand and the price correspondingly shot up. Our facilities outside China also rallied to help our colleagues secure 3-ply masks.ASE mask factoryMask-wearing reduces the spread of viral particles from asymptomatic carriers and plays a key role in mitigating the spread of COVID-19.ASE has invested in the production of high-quality surgical masks at ASE Kaohsiung.ASE medical grade masks have received certification from Taiwan’s Ministry of Health and Welfare.- protecting the health of our employees - ensuring easy access to masksASESG reusable masksAt ASE Singapore, employees are provided custom designed ASE-logo reusable masks. The fabric masks are made from high quality material and each has an insert for filters that retain their efficacy after repeated washes.To ensure that customers are kept abreast of the developments and to minimize any disruptions, we posted daily updates on each facility on our official website during the height of the pandemic. In parallel, individual sites kept their respective customers updated frequently and drew up contingency plans to mitigate impact to customers.Importantly, we all recognized the need to play our part to prevent the spread of the disease. Temperature checks, travel history and health declaration became mandatory for all employees and visitors to ASE premises. Social distancing emerged as a new buzz phrase, but it is proving an effective preventive measure. Thanks to modern technology, we were able to conduct video and conference calls with colleagues, customers and suppliers with little disruption to business.In the months of March and April, many countries worldwide imposed some sort of lockdowns as the outbreak worsened outside China. As a result, many of our offices rolled out ‘work from home’ schemes, as well as alternate team work arrangements to minimize large group gatherings. Today, our operations in Asia have returned to normalcy. Our US and Europe colleagues, however, are still requested to work from home until the situation improves.The pandemic has caused huge disruptions and forced us to rethink how we work, interact, and socialize. For now, we’re all staying put where we are, and hopefully spending quality time with family while keeping ourselves healthy, both physically and mentally. Until we find a vaccine or a cure, we have to embrace the new norm as best as we can.Wash your handsWear a maskWiden your space
Jennifer Yuen 9/15/2020 ESG

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